HD404364 查看數據表（PDF） - Renesas Electronics
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HD404364 Datasheet PDF : 117 Pages
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HD404369 Series
System clock selection register 1 (SSR1: $027)
Bit
Initial value
Read/Write
Bit name
3
2
0
0
W
W
SSR13*1 SSR12
1
0
0
—
W
—
SSR11*2 Not used
SSR11
0
1
System Clock Selection
0.4 to 1.0 MHz
1.6 to 5.0 MHz (HD404369 Series)
1.6 to 8.5 MHz (HD40A4369 Series)
SSR12
0
1
32-kHz Oscillation Division
Ratio Selection
fSUB = fX/8
fSUB = fX/4
Notes:
SSR13 32-kHz Oscillation Stop
0
Oscillation operates in stop mode
1
Oscillation stops in stop mode
1. SSR13 will only be cleared to 0 by a RESET input. A STOPC input during stop mode will
not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode.
2. If fOSC = 0.4 to 1.0 MHz, SSR11 must be set 0; if fOSC = 1.6 to 8.5 MHz, SSR11 must be set to
1. Do not use fOSC = 1.0 to 1.6 MHz with 32-kHz oscillation.
Figure 23 System Clock Selection Register 1 (SSR1)
System Clock Selection Register 2 (SSR2: $028): Four bit write-only register which is used to select the
system clock divisor (figure 24).
The division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1
(SSR20, SSR21) of system clock select register 2 (SSR2).
The values of SSR20 and SSR21 are valid after the MCU enters watch mode. The system clock must be
stopped when the division ratio is to be changed.
There are two methods for changing the system clock divisor, as follows.
• In active mode, set the divisor by writing to SSR20 and SSR21. At this point, the prior divisor setting
will remain in effect. Now, switch to watch mode, and then return to active mode. When active mode
resumes, the system clock divisor will have switched to the new value.
• In subactive mode, set the divisor by writing to SSR20 and SSR21. Then return to active mode through
watch mode. When active mode resumes, the system clock divisor will have switched to the new value.
(The change will also take effect for direct transition to active mode.)
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