HD404374 查看數據表（PDF） - Renesas Electronics

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HD404374

Low-Voltage AS Microcomputers with On-Chip A/D Converter

Renesas Electronics 

HD404374/HD404384/HD404389/HD404082/HD404084 Series

Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD

instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not

affected by any other instructions.

The following restrictions apply to individual bits.

IE

IM

LSON *1

IF

ICSF

ICEF

GEF

RSP

WDON

ADSF *2

DTON *1

Not Used

SEM/SEMD

Allowed

Not executed

Allowed

Not executed

Allowed

Allowed

Not executed in active mode

Used in subactive mode

Not executed

REM/REMD

Allowed

Allowed

Allowed

Allowed

Not executed

Inhibited

Allowed

Not executed

TM/TMD

Allowed

Allowed

Inhibited

Inhibited

Inhibited

Allowed

Allowed

Inhibited

Notes : The WDON bit is reset only by stop mode clearance by means of an MCU reset.

Do not use the REM or REMD instruction on the ADSF bit during A/D conversion.

The DTON bit is always in the reset state in active mode.

If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent

bit, the status flag value will be undetermined

* 1 Applies to HD404374 Series.

* 2 Applies to HD404374, HD404384, and HD404389 Series.

Figure 4 Instruction Restrictions

Rev.5.00, Sep.11.2003, page 28 of 161

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