H8/3004 查看數據表（PDF） - Renesas Electronics

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产品描述 (功能)

生产厂家

H8/3004

Microcomputer

Renesas Electronics 

Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the

T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to

the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The

address bus outputs are held during the T3 state.The same timing applies when a reset occurs in

the T2 state of an access cycle to a two-state-access area.

Access to external address

T1

T2

T3

ø

RES

Internal

reset signal

Address bus

(mode 1)

AS (mode 1)

RD (read access)

(mode 1)

WR (write access)

(mode 1)

Data bus

(write access)

(mode 1)

I/O port

(modes 1, 3)

H'000000

High impedance

High impedance

Figure D-3 Reset during Memory Access (Reset during T3 State)

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