HD64570F 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HD64570F

Serial Communications Adaptor

Hitachi -> Renesas Electronics 

1.4 Block Diagram

INT

INTA

HOLD/BUSREQ

HOLDA/BUSACK

BUSY

BEO

WAIT

CS

WR/ R/W

RD/N.C.

AS

BHE/HDS

A0 /LDS

A1 to A23

D0 to D15

RESET

CPU0

CPU1

Inter-

rupt

con-

troller

Bus

Arbi-

ter

Wait

con-

troller

Bus

inter-

face

Timers

(4 channels)

Internal bus

DMAC (direct

memory

access

controller)

φ

MSCI

(multiprotocol

serial

communication

interface)

[channel 0]

MSCI

(multiprotocol

serial

communication

interface)

[channel 1]

CLK

Clock

generator

φ : Internal clock (synchronized with CLK in

CPU modes 1, 2, and 3; inverted CLK in

mode 0)

Figure 1.1 Block Diagram of SCA

SYNC0

TXD0

RXD0

TXC0

RXC0

RTS0

DCD0

CTS0

SYNC1

TXD1

RXD1

TXC1

RXC1

RTS1

DCD1

CTS1

VCC

VSS

Rev. 0, 07/98, page 4 of 453

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