HDM8513 查看數據表（PDF） - Hynix Semiconductor

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HDM8513

DVB/DSS Compliant Receiver

Hynix Semiconductor 

TABLE OF CONTENTS

1. INTRODUCTION TO THE HDM8513A................................................................................................................6

1.1 FEATURES AND BENEFITS..................................................................................................................................7

2. HARDWARE SPECIFICATION..............................................................................................................................8

3. TECHNICAL OVERVIEW..................................................................................................................................... 18

3.1 DUAL CHANNEL ANALOG TO DIGITAL CONVERTER .................................................................................. 18

3.2 VARIABLE RATE DEMODULATOR.................................................................................................................. 20

3.3 NOISE MEASUREMENT CIRCUIT .....................................................................................................................22

3.4 VITERBI DECODER.............................................................................................................................................24

3.5 AUTONOMOUS ACQUISITION..........................................................................................................................25

3.6 REED SOLOMON DECODER.............................................................................................................................. 27

3.7CLOCK GENERATION PLL .................................................................................................................................29

3.8 DBS RECEIVER................................................................................................................................................... 30

4. MECHANICAL SPECIFICATIONS..................................................................................................................... 31

4.1 100 PIN QUAD FLAT PACK................................................................................................................................31

4.2 64 PIN THIN QUAD FLAT PACK........................................................................................................................33

4.3 RECOMMENDED ANALOG PIN CONNECTION............................................................................................... 35

4.4 RECOMMENDED CLOCK GENERATION CIRCUIT...........................................................................................35

5. SIGNAL DESCRIPTION....................................................................................................................................... 36

5.1 INPUTS..................................................................................................................................................................36

5.2 OUTPUTS............................................................................................................................................................. 36

5.3 M ONITOR AND CONTROL INTERFACE ...........................................................................................................39

5.4 I2C MODE............................................................................................................................................................. 40

6. REGISTER DEFINITIONS..................................................................................................................................... 42

6.1 W RITE REGISTERS..............................................................................................................................................42

6.2 READ REGISTERS................................................................................................................................................55

APPENDIX.................................................................................................................................................................... 58

A1. LOOP FILTER PROGRAMMING APPLICATION NOTE................................................................................59

A2. FALSE LOCK ESCAPE APPLICATION NOTE .................................................................................................62

A3. PERFORMANCE WITH INTERFERENCE.......................................................................................................... 63

A4. NYQUIST CRITERIA CONSIDERATIONS......................................................................................................... 67

LIST OF FIGURES

FIGURE 1: TOP LEVEL BLOCK DIAGRAM....................................................................................................................6

FIGURE 2: INPUT DATA TIMING DIAGRAM ...............................................................................................................9

FIGURE 3: INTEL 80C88A READ TIMING DIAGRAM............................................................................................... 10

FIGURE 4: INTEL 80C88A WRITE TIMING DIAGRAM............................................................................................. 11

FIGURE 5: INTEL 8051 READ TIMING DIAGRAM .....................................................................................................12

FIGURE 6: INTEL 8051 WRITE TIMING DIAGRAM...................................................................................................13

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