HMP8115CN 查看數據表（PDF） - Intersil

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HMP8115CN

NTSC/PAL Video Decoder

Intersil 

HMP8115

CLK

DVALID

BLANK

P[15-8]

Cb0

Y0

Cr0

Y1

Cb2

Y2

Cr2

Y3

Cb4

Y4

NOTE:

tDVLD

8. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate

every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to

blanking levels.

FIGURE 10. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)

CLK

DVALID

BLANK

P[15-8]

Cb0

Y0

Cr0

Y1

Cb2

Y2

Cr2

Y3

Cb4

Y4

NOTES:

tDVLD

9. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate

every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to

blanking levels.

10. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will stay low during active video and

be gated with the clock only during the blanking interval.

FIGURE 11. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)

16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT

In these output modes, DVALID may be configured to oper-

ate in one of four modes as controlled by the DVLD_LTC and

DVLD_DCYC bits of the GENLOCK CONTROL register

(04H). Bit 4 is the DVLD_LTC bit and bit 5 is the

DVLD_DCYC bit.

If DVLD_LTC=0 and DVLD_DCYC=0, DVALID is present

only during the active video time on active scan lines. Thus,

DVALID being asserted indicates valid pixel data is present

on the P0-P15 pixel outputs. DVALID is never asserted dur-

ing the blanking intervals. In this mode DVALID will have a

50% duty cycle only during the active video times. The tim-

ing diagrams for this mode can be found in Figures 12 and

13.

If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the

same as the first mode, with the exception that DVALID does

not have a 50% duty cycle. This mode is intended for back-

ward compatibility with HMP8112(A) timing dependencies in

which DVALID did not have a 50% duty cycle timing and

other timing variations. The timing diagrams for this mode

can be found in Figures 14 and 15.

If DVLD_LTC=1 and DVLD_DCYC=0, DVALID is present the

entire line time on all scan lines. DVALID may occasionally

be negated for two consecutive CLK2 cycles just prior to

active video. In this mode DVALID is guaranteed have a 50%

duty cycle only during the active video times. The timing for

this mode differs from the timing shown in Figures 12 and 13

only in that DVALID will also be asserted during the blanking

portion of the video line time as described above.

If DVLD_LTC=1 and DVLD_DCYC=1, DVALID is present

during the entire line time on all scan lines. DVALID is

asserted during the blanking intervals as needed to ensure a

constant number of total samples per line. The timing for this

mode differs from the timing shown in Figures 14 and 15

only in that DVALID will also be asserted during the blanking

portion of the video line time as described above.

12

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