HMP8171EVAL1 查看數據表（PDF） - Intersil
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HMP8171EVAL1 Datasheet PDF : 33 Pages
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HMP8170, HMP8171, HMP8172, HMP8173
SDA
SCL
S
1-7
8
9
1-7
8
START
CONDITION
ADDRESS
R/W
ACK
DATA
FIGURE 10. I2C SERIAL TIMING FLOW
9
ACK
DATA WRITE
S
DATA READ
CHIP ADDR
0x40 OR
0x42
A SUB ADDR
A
DATA
REGISTER
POINTED
TO BY
SUBADDR
A
DATA
AP
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
S CHIP ADDR
0x40 OR
0x42
A SUB ADDR A S
CHIP ADDR
0x41 OR
0x43
A DATA
A DATA
NA P
REGISTER
POINTED
TO BY
SUBADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
P
STOP
CONDITION
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
FROM MASTER
FROM ENCODER
BIT
NUMBER
FUNCTION
7-0
Product ID
FIGURE 11. REGISTER WRITE PROGRAMMING FLOW
TABLE 14. PRODUCT ID REGISTER
SUB ADDRESS = 00H
DESCRIPTION
This 8-bit register specifies the last two digits of the product number. It is a read-only register.
Data written to it is ignored.
RESET
STATE
70H
71H
72H
73H
BIT
NUMBER
FUNCTION
7-5
Video Timing
Standard
4-3
Output Format
2-0
NTSC / PAL
Setup Select
TABLE 15. OUTPUT FORMAT REGISTER
SUB ADDRESS = 01H
DESCRIPTION
000 = (M) NTSC
001 = reserved
010 = (B, D, G, H, I) PAL
011 = (M) PAL
100 = (N) PAL
101 = (NC) PAL
110 = reserved
111 = reserved
00 = Composite + Y/C
01 = Composite + YUV (HMP8172 and HMP8173 only)
10 = Composite + RGB without sync on green (HMP8172 and HMP8173 only)
11 = Composite + RGB with sync on green (HMP8172 and HMP8173 only)
These bits specify the blanking pedestal during active video, from 0 IRE (“000”) to 7.5 IRE
(“111”). Typically, these bits should be a “111” during (M) NTSC and (M, N) PAL operation.
Otherwise, they should be a “000”. These bits do not affect the analog RGB or YUV outputs.
RESET
STATE
000B
00B
111B
15
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