HSP43881 查看數據表（PDF） - Intersil

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HSP43881

Digital Filter

Intersil 

HSP43881

Cascade Configuration

To design a filter length L>8, L/8 DFs are cascaded by

connecting the COUT0-7 outputs of the (i)th DF to the CIN0-

7 inputs of the (i+1)th DF. The DIN0-7 inputs and SUM0-25

outputs of all the DFs are also tied together. A specific

example of two cascaded DFs illustrates the technique

(Figure 5). Timing (Figure 6) is similar to the simple 8-tap

FIR, except the ERASE and SENBL/SENBH signals must be

enabled independently for the two DFs in order to clear the

correct accumulators and enable the SUM0-25 output

signals at the proper times.

Single DF Configuration

Using a single DF, a filter of length L>8 can be constructed

by processing in L/8 passes as illustrated in the following

table (Table 2) for a 16-tap FIR. Each pass is composed of

Tp = 7 + L cycles and computes eight output samples. In

pass i, the sample with indices i*8 to i*8 +(L1) enter the

DIN0-7 inputs. The coefficients C0 -CL -1 enter the CIN0-7

inputs, followed by seven zeros. As these zeros are entered,

the result samples are output and the accumulators reset.

Initial filing of the pipeline is not shown in this sequence

table. Filter outputs can be put through a FIFO to even out

the sample rate.

Extended Coefficient and Data Sample

Word Size

The sample and coefficient word size can be extended by

utilizing several DFs in parallel to get the maximum sample

rate or a single DF with resulting lower sample rates. The

technique is to compute partial products of 8 x 8 and

combine these partial products by shifting and adding to

obtain the final result. The shifting and adding can be

accomplished with external adders (at full speed) or with the

DF's shift and add mechanism contained in its output stage

(at reduced speed).

Decimation/Resampling

The HSP43881 DF provides a mechanism for decimating by

factors of 2, 3, or 4. From the DF filter cell block diagram

(Figure 1), note the three D registers and two multiplexers in

the coefficient path through the cell. These allow the

coefficients to be delayed by 1, 2, or 3 clocks through the

cell. The sequence table (Table 3) for a decimate by two filter

illustrates the technique (internal cell pipelining ignored for

simplicity).

Detailed timing for a 30MHz input sample rate, 15MHz

output sample rate (i.e., decimate by two), 16-tap FIR filter,

including pipelining, is shown in Figure 7. This filter requires

only a single HSP43881 DF.

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