HT46R62 查看數據表（PDF） - Holtek Semiconductor

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HT46R62

A/D with LCD Type 8-Bit MCU

Holtek Semiconductor 

HT46R62/HT46C62

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RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES Wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT Wake-up HALT

Note: ²u² stands for unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state or during power up.

Awaking from the HALT state or system power-up, the

SST delay is added.

An extra SST delay is added during the power-up pe-

riod, and any wake-up from HALT may enable only the

SST delay.

The functional unit chip reset status is shown below.

Program Counter

000H

Interrupt

Disabled

Prescaler, Divider

Cleared

WDT, RTC, Time Base

Cleared. After master reset,

WDT starts counting

Timer/event Counter Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

VDD

RES

S S T T im e - o u t

C h ip R e s e t

tS S T

Reset Timing Chart

H A LT

W DT

RES

W DT

T im e - o u t

R eset

O SC1

SST

1 0 - b it R ip p le

C o u n te r

E x te rn a l

W a rm R e s e t

C o ld

R eset

P o w e r - o n D e te c tio n

Reset Configuration

Timer/Event Counter

One timer/event counters (TMR) are implemented in the

microcontroller. The Timer/Event Counter contains a

8-bit programmable count-up counter and the clock may

come from an external source or an internal clock

source. An internal clock source comes from fSYS. The

external clock input allows the user to count external

events, measure time intervals or pulse widths, or to

generate an accurate time base.

There are two registers related to the Timer/Event

Counter; TMR ([0DH]) and TMRC ([0EH]). Two physical

registers are mapped to TMR location; writing TMR puts

the starting value in the Timer/Event Counter register

and reading TMR takes the contents of the Timer/Event

Counter. The TMRC is a timer/event counter control reg-

ister, which defines some options counting enable or

disable and an active edge.

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

mode can be used to count the high or low level duration

of the external signal (TMR), and the counting is based

on the internal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (TF; bit 6 of INTC0). In the pulse width mea-

surement mode with the values of the TON and TE bits

equal to 1, after the TMR has received a transient from

low to high (or high to low if the TE bit is ²0²), it will start

counting until the TMR returns to the original level and

resets the TON. The measured result remains in the

timer/event counter even if the activated transient oc-

curs again. In other words, only 1-cycle measurement

can be made until the TON is set. The cycle measure-

ment will re-function as long as it receives further tran-

sient pulse. In this operation mode, the timer/event

counter begins counting not according to the logic level

but to the transient edges. In the case of counter over-

Rev. 1.60

15

July 14, 2005

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