HT46R62 查看數據表（PDF） - Holtek Semiconductor
零件编号
产品描述 (功能)
生产厂家
HT46R62 Datasheet PDF : 46 Pages
| |||
HT46R62/HT46C62
D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
C o n tr o l B it
DQ
P u ll- h ig h
O p tio n
CK Q
S
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2
B Z /B Z /P F D /P W M 0 /P W M 1 /P W M 2
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
IN T 0 fo r P D 4 o n ly
IN T 1 fo r P D 5 o n ly
T M R fo r P D 6 o n ly
D a ta B it
DQ
CK Q
S
M
U
X
M
U
X
PFD EN
(P A 3 )
W a k e - u p O p tio n s
Input/Output Ports
V DD
P A 0 /B Z
P A 1 /B Z
PA2
P A 3 /P F D
P A 4~P A 7
P B 0 /A N 0 ~ P B 5 /A N 5
P D 0 /P W M 0
P D 1 /P W M 1
P D 2 /P W M 2
P D 4 /IN T 0
P D 5 /IN T 1
P D 6 /T M R
on PD0/PD1/PD2 (if PD0/PD1/PD2 is operating in out-
put mode). The I/O functions of PD0/PD1/PD2 are as
shown.
I/O
I/P
O/P
Mode (Normal) (Normal)
PD0
PD1
PD2
Logical
Input
Logical
Output
I/P
(PWM)
Logical
Input
O/P
(PWM)
PWM0
PWM1
PWM2
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
Timer
Preload
Value
PA3 Data
Register
PA3 Pad
State
PFD
Frequency
OFF X
0
0
X
OFF X
1
U
X
ON
N
0
0
X
ON
N
1
PFD fTMR/[2´(M-N)]
Note:
²X² stands for unused
²U² stands for unknown
²M² is ²256² for PFD
²N² is preload value for timer/event counter
²fTMR² is input clock frequency for timer/event
counter
PWM
The microcontroller provides 3 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1/PD2. The PWM channels have their data reg-
isters denoted as PWM0 (1AH), PWM1 (1BH) and
PWM2 (1CH). The frequency source of the PWM coun-
ter comes from fSYS. The PWM registers are three 8-bit
registers. The waveforms of PWM outputs are as
shown. Once the PD0/PD1/PD2 are selected as the
PWM outputs and the output function of PD0/PD1/PD2
are enabled (PDC.0/PDC.1/ PDC.2=²0²), writing ²1² to
PD0/PD1/PD2 data register will enable the PWM output
function and writing ²0² will force the PD0/PD1/PD2 to
stay at ²0².
A (6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
Modulation cycle i
(i=0~3)
AC (0~3)
i<AC
i³AC
Duty Cycle
DC + 1
64
DC
64
Rev. 1.60
19
July 14, 2005
Share Link: 