HT46R62 查看數據表（PDF） - Holtek Semiconductor
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HT46R62 Datasheet PDF : 46 Pages
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HT46R62/HT46C62
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
Modulation cycle i
(i=0~1)
AC (0~1)
i<AC
i³AC
Duty Cycle
DC + 1
128
DC
128
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
PWM Cycle PWM Cycle
Modulation Frequency Frequency Duty
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
fSYS/256
[PWM]/256
fS Y S /2
[P W M ] = 1 0 0
PW M
2 5 /6 4
2 5 /6 4
2 5 /6 4
[P W M ] = 1 0 1
PW M
2 6 /6 4
2 5 /6 4
[P W M ] = 1 0 2
PW M
2 6 /6 4
2 6 /6 4
[P W M ] = 1 0 3
PW M
2 6 /6 4
2 6 /6 4
P W M m o d u la tio n p e r io d : 6 4 /fS Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
2 5 /6 4
2 5 /6 4
2 6 /6 4
M o d u la tio n c y c le 2
P W M c y c le : 2 5 6 /fS Y S
(6+2) PWM Mode
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
M o d u la tio n c y c le 3
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
M o d u la tio n c y c le 0
fS Y S /2
[P W M ] = 1 0 0
PW M
[P W M ] = 1 0 1
PW M
[P W M ] = 1 0 2
PW M
[P W M ] = 1 0 3
PW M
Rev. 1.60
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
P W M m o d u la tio n p e r io d : 1 2 8 /fS Y S
M o d u la tio n c y c le 0
P W M c y c le : 2 5 6 /fS Y S
5 1 /1 2 8
M o d u la tio n c y c le 1
(7+1) PWM Mode
20
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
M o d u la tio n c y c le 0
July 14, 2005
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