HT82V46 查看數據表（PDF） - Holtek Semiconductor
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HT82V46 Datasheet PDF : 27 Pages
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HT82V46
VIN
VRL
CDS
VRLC
Input
Sampling
Block
Offset
DAC
Block
PGA
Block
ADC
Block
+
V1
+
-
+
V2
+
+
+
x
V3 +
* 65535 / VFS
Output
Invert
Block
D1
D2
OD[7:0]
=1
Offset
=0
DAC
= 0X : + 32768
= 10 : + 65535
= 11 : + 0
2
PGAFS[1:0]
= 0 : D2 = D1
= 1 : D2 = 65535– D1
INVOD
CDACPD
RLC
4
DAC
9
0.66 + PGA[8:0] * 7.34 / 511
8
260mV * (DAC[7:0]–127.5) / 127.5
CDAC[3:0]
Where
VIN = VINR or VING or VINB
VRL = VIN sampled during Ref. clamp
VRLC = voltage applied to VRLC/VBIAS pin
Figure 13 Overall Signal Flow
ADCK
WS = 0
ODFM[1:0] = X0
OD[7:0]
ODFM[1:0] = 01
OD[7:0]
WS = 1
ODFM[1:0] = X0
OD[7:0]
ODFM[1:0] = 01
OD[7:0]
ODFM[1:0] = 11
OD[7:4]
t OD
tOD
HB LB HB LB HB LB HB LB HB LB HB LB
HB
HB
HB
HB
HB
HB
HB
LB
HB
LB
HB
LB
HB
HB
HB
NB4 NB3 NB2 NB1 NB4 NB3 NB2 NB1 NB4 NB3 NB2
HB : High Byte; LB : Low Byte
NB4~NB1 : Nibble (NB4 is the most significant)
Figure 14 Output Data Format
Rev. 1.10
16
November 24, 2011
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