IC42S32200-8B 查看數據表（PDF） - Integrated Circuit Systems

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IC42S32200-8B

512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Circuit Systems 

IC42S32200

IC42S32200L

CLK

CKE

CS#

RAS#

CAS#

WE#

ADDR.

DQM

DQ Hi-Z

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

tCK2

Clock min.

Address Key

tRP

Precharge All

Mode Register Any

Set Command Command

Mode Register Set Cycle

The mode register is divided into various fields depending on functionality.

Address BS0,1 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU* RFU* WBL Test Mode

CAS Latency

BT

Burst Length

*Note:RFU (Reserved for future use)should stay 0 during MRS cycle.

• Burst Length Field (A2~A0)

This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2,

4,8,or full page.

A2 A1

A0 Burst Length

00

0

1

00

1

2

01

0

4

01

1

8

10

0

Reserved

10

1

Reserved

11

0

Reserved

11

1

Full Page

16

Integrated Circuit Solution Inc.

DR036-0D 02/04/2005

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