CS853014BGLFT 查看數據表（PDF） - Integrated Device Technology

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CS853014BGLFT

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Integrated Device Technology 

ICS853014

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information, continued

PCLKx

PCLKx

EN

t SET-UP

tHOLD

Setup and Hold Time

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VCC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and

R2/R1 = 0.609.

Single Ended Clock Input

VCC

R1

1K

PCLKx

V_REF

C1

0.1u

nPCLKx

R2

1K

Figure 2. Single-Ended Signal Driving Differential Input

IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

9

ICS853014BG REV. DNOVEMBER 12, 2007

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