AV9248-64 查看數據表（PDF） - Integrated Circuit Systems

零件编号

产品描述 (功能)

生产厂家

AV9248-64

AMD-K7™ System Clock Chip

Integrated Circuit Systems 

ICS9248-64

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.

CPU_STOP# is synchronized by the ICS9248-64. All other clocks will continue to run while the CPUCLKs clocks are

disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width

is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

INTERNAL

CPUCLK

PCICLK

CPU_STOP#

PCI_STOP# (High)

PD# (High)

CPUCLKT

CPUCLKC

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist.

This signal is synchronized to the CPUCLKs inside the ICS9248-64.

3. All other clocks continue to run undisturbed including SDRAMR.

4. PD# and PCI_STOP# are shown in a high (true) state.

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