ICS932S202 查看數據表（PDF） - Integrated Circuit Systems
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ICS932S202
Integrated Circuit Systems
ICS932S202 Datasheet PDF : 14 Pages
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ICS932S202
General Description
The ICS932S202 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs.This
chip provides all the clocks required for such a system.
Spread Spectrum may be enabled through I2C. Spread spectrum typically reduces system EMI by 8dB to 10dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding.The ICS932S202 employs
a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Pin Descriptions
Pin number
Pin name
1, 7, 13, 19, 25,
31, 36, 41, 45
GND
2
REF0
REF1
3
SEL24_48
4, 10, 16, 23, VDD
28, 35
5
X1
6
X2
8
PCICLK0
FS0
9
PCICLK1
FS1
PCICLK2
11
FS2
12
PCICLK3
FS3
22, 21, 20, 18,
17, 15, 14
PCICLK (10:4)
24
PD#
26
27
29
30
34, 33, 32
38, 37
40, 42
39, 43
44, 46, 47
48
24_48MHz
48MHz
FS4
SCLK
SDATA
3V66 (2:0)
CPU_CSCLK (1:0)
CPUCLK (1:0)
VDDLCPU
IOAPIC (2:0)
VDDLAPIC
0600A—08/04/03
Type
Description
PWR Ground pins
OUT
OUT
IN
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
PWR Power pins 3.3V
IN
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks.
IN
OUT
OUT/IN
IN
IN
I/O
OUT
OUT
OUT
PWR
OUT
PWR
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the
output clocks are held at a Low state.
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output. 3.3V
Logic - input for frequency selection
Clock input of I2C input
Data pin for I2C circuitry 5V tolerant
3.3V clock outputs. These outputs are stopped when
CPU_STOP# is driven active..
Chipset clock outputs @ 2.5V
CPU clock outputs @ 2.5V.
Power pins for CPUCLKs. 2.5V
IOAPIC clocks @ 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
2
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