ICS9LPRS462 查看數據表（PDF） - Integrated Device Technology
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ICS9LPRS462
Integrated Device Technology
ICS9LPRS462 Datasheet PDF : 23 Pages
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ICS9LPRS462
Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
Absolute Max
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Input Supply
Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection HBM
SYMBOL
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
CONDITIONS
-
-
-
-
-
-
MIN
GND -
0.5
-65
0
2000
TYP
MAX
VDD + 0.5V
VDD + 0.5V
150
70
115
UNITS
V
V
°C
°C
°C
V
Notes
1
1
1
1
1
1
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Current
VIH
VIL
IIH
IIL1
IIL2
VIH_FS
3.3 V +/-5%
2
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VSS - 0.3
-5
-5
VIN = 0 V; Inputs with pull-up
resistors
-200
3.3 V +/-5%
0.7
VIL_FS
IDD3.3OP
3.3 V +/-5%
9LPRS462, all outputs driven
9LPRS464, all outputs driven
VSS - 0.3
VDD + 0.3
V
1
0.8
V
1
5
uA
1
uA
1
uA
1
VDD + 0.3
V
1
0.35
V
1
200
mA
1
180
mA
1
Powerdown Current
IDD3.3PD
all diff pairs low/low
21
Input Frequency
Fi
VDD = 3.3 V
14.31818
Pin Inductance
Lpin
7
CIN
Logic Inputs
5
Input Capacitance
COUT
Output pin capacitance
6
CINX
X1 & X2 pins
5
Clk Stabilization
TSTAB
From VDD Power-Up or de-
assertion of PD to 1st clock
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_PD
CPU output enable after
PD de-assertion
300
Tfall_PD
PD fall time of
5
mA
1
MHz
2
nH
1
pF
1
pF
1
pF
1
ms
1
kHz
1
us
1
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
VDD
2.7
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
Current sinking at
VOL = 0.4 V
IPULLUP
4
SMBCLK/SMBDAT
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
SMBCLK/SMBDAT
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
0.4
1000
300
V
1
mA
1
ns
1
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL
outputs.
IDTTM/ICSTM Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
1378A—04/07/08
5
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