IDT7005S17F 查看數據表（PDF） - Integrated Device Technology

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IDT7005S17F

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)

Symbol

Parameter

IDT7005X15 IDT7005X17

Com'l. Only Com'l. Only

Min. Max. Min. Max.

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

— 15 —

17

tBDA

BUSY Disable Time from Address Not Matched — 15 —

17

tBAC

BUSY Access Time from Chip Enable Low

— 15 —

17

tBDC

tAPS

tBDD

tWH

BUSY Disable Time from Chip Enable High

— 15 —

17

Arbitration Priority Set-up Time(2)

5—5

—

BUSY Disable to Valid Data(3)

— 18 —

18

Write

Hold

After

(5)

BUSY

12 — 13

—

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write

Hold

After

(5)

BUSY

0 —0

—

12 — 13

—

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

— 30 —

30

— 25 —

25

IDT7005X20

Min. Max.

—

20

—

20

—

20

—

17

5

—

—

30

15

—

0

—

15

—

—

45

—

35

IDT7005X25

Min. Max. Unit

—

20 ns

—

20 ns

—

20 ns

—

17 ns

5

— ns

—

30 ns

17

— ns

0

— ns

17

— ns

—

50 ns

—

35 ns

Symbol

Parameter

IDT7005X35

Min. Max.

IDT7005X55

Min. Max.

IDT7005X70

Mil. Only

Min. Max. Unit

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

—

20

—

45

—

45 ns

tBDA

BUSY Disable Time from Address Not Matched

—

20

—

40

—

40 ns

tBAC

BUSY Access Time from Chip Enable Low

—

20

—

40

—

40 ns

tBDC

tAPS

tBDD

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time(2)

BUSY Disable to Valid Data(3)

—

20

—

35

—

35 ns

5

—

5

—

5

— ns

—

35

—

40

—

45 ns

tWH

Write

Hold

After

(5)

BUSY

25

—

25

—

25

— ns

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write

Hold

After

(5)

BUSY

0

—

0

—

0

— ns

25

—

25

—

25

— ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

60

—

80

—

95 ns

—

45

—

65

—

80 ns

NOTES:

2738 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. "X" in part numbers indicates power rating (S or L).

6.06

12

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