IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH BUSY (M/S = VIH)(2,4,5)
tWC
ADDR"A"
W R/ "A"
MATCH
tWP
tDW
tDH
DATAIN "A"
tAPS (1)
VALID
ADDR"B"
BUSY"B"
MATCH
tBDA
tBDD
DATAOUT "B"
tWDD
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
VALID
2738 drw 13
TIMING WAVEFORM OF WITH WRITE BUSY
W R/ "A"
BUSY"B"
tWP
tWB(3)
W R/ "B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
tWH (1)
2738 drw 14
6.06
13