IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5)
tWC
ADDR"A"
W R/ "A"
MATCH
tWP
tDW
tDH
DATAIN "A"
tAPS (1)
VALID
ADDR"B"
MATCH
BUSY"B"
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".
VALID
2739 drw 13
TIMING WAVEFORM OF WRITE WITH BUSY
W R/ "A"
BUSY"B"
tWP
tWB (3)
tWH (1)
W R/ "B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B" blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
2739 drw 14
6.07
13