IDT7006S17JB 查看數據表（PDF） - Integrated Device Technology
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IDT7006S17JB Datasheet PDF : 20 Pages
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IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
BUSY"B"
tBDC
2739 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
tAPS (2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2739 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
Symbol
Parameter
IDT7006X15
Com'l. Only
Min. Max.
IDT7006X17
Com'l. Only
Min. Max.
IDT7006X20
Min. Max.
INTERRUPT TIMING
tAS
Address Set-up Time
0
—
0
—
0
—
tWR
Write Recovery Time
—
0
0
—
0
—
tINS
Interrupt Set Time
—
15
—
15
—
20
tINR
Interrupt Reset Time
—
15
—
15
—
20
IDT7006X25
Min. Max. Unit
0
— ns
0
— ns
—
20 ns
—
20 ns
Symbol
Parameter
INTERRUPT TIMING
tAS
Address Set-up Time
tWR
Write Recovery Time
tINS
Interrupt Set Time
tINR
Interrupt Reset Time
NOTE:
1. "X" in part numbers indicates power rating (S or L).
IDT7006X35
Max. Min.
IDT7006X55
Max. Min.
IDT7006X70
Mil. Only
Max. Unit
0
—
0
—
0
— ns
0
—
0
—
0
— ns
—
25
—
40
—
50 ns
—
25
—
40
—
50 ns
2739 tbl 16
6.07
14
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