IDT71V432 查看數據表（PDF） - Integrated Device Technology

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IDT71V432

32K x 32 CacheRAM™ 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect

Integrated Device Technology 

IDT71V432, 32K x 32 CacheRAM

3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range (VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)

Symbol

Parameter

Test Conditions

Min.

Max. Unit

|ILI|

Input Leakage Current

VDD = Max., VIN = 0V to VDD

|ILI|

ZZ and LBO Input Leakage Current(1) VDD = Max., VIN = 0V to VDD

—

5

µA

—

30

µA

|ILO|

Output Leakage Current

CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max.

—

5

µA

VOL

Output Low Voltage (I/O1–I/O31)

IOL = 5mA, VDD = Min.

—

0.4

V

VOH

Output High Voltage (I/O1–I/O31)

IOH = –5mA, VDD = Min.

2.4

—

V

NOTE:

3104 tbl 12

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range(1) (VDD = 3.3V +10/-5%, VHD = VDD–0.2V, VLD = 0.2V)

IDT71V432S5 IDT71V432S6 IDT71V432S7

Symbol

Parameter

Test Conditions

Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit

IDD Operating Power Supply Current

Device Selected, Outputs Open, VDD = Max.,

VIN > VIH or < VIL, f = fMAX(2)

200 200 180 180 160 160 mA

ISB Standby Power Supply Current

Device Deselected, Outputs Open, VDD = Max., 65 65 60 60 55 55 mA

VIN > VIH or < VIL, f = fMAX(2)

ISB1 Full Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max., 15 15 15 15 15 15 mA

VIN > VHD or < VLD, f = 0(2)

IZZ Full Sleep Mode Power Supply Current ZZ > VHD, VDD = Max.

10 10 10 10 10 10 mA

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3104 tbl 13

AC Test Loads

+3.3V

+1.5V

50Ω

I/O

Z0 = 50Ω

I/O

351Ω

317Ω

5pF*

Figure 1. AC Test Load

3104 drw 03

6

5

4

∆tCD

3

(Typical, ns) 2

1

20 30 50 80 100

Capacitance (pF)

200

3104 drw 05

Figure 3. Lumped Capacitive Load, Typical Derating

* Including scope and jig capacitance.

3104 drw 04

Figure 2. AC Test Load

(for tOHZ, tCHZ, tOLZ, and tDC1)

AC Test Conditions

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

6.482

0 to 3.0V

2ns

1.5V

1.5V

See Figures 1 and 2

3104 tbl 14

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