IDT72V3673(2016) 查看數據表（PDF） - Integrated Device Technology

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IDT72V3673
(Rev.:2016)

3.3 VOLT CMOS SyncFIFO™ WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol

MBA

MBB

Name

Port A Mailbox

Select

Port B Mailbox

Select

MBF1

Mail1 Register Flag

MBF2

Mail2 Register Flag

RS1, RS2 Resets

PRS/

Partial Reset/

RT

Retransmit

RTM

SIZE(1)

W/RA

W/RB

Retransmit Mode

Bus Size Select

(Port B)

Port A Write/

Read Select

Port B Write/

Read Select

I/O

Description

I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.

I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the

B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and

a LOW level selects FIFO data for output.

O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.

Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-

HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH

following either a Reset (RS1) or Partial Reset (PRS).

O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.

Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-

HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH

following either a Reset (RS2) or Partial Reset (PRS).

I A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and

sets the Port B output register to all zeroes. A LOW-to-HIGH transition on RS1 selects the programming

method (serial or parallel) and one of five programmable flag default offsets. It also configures Port

B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-

HIGH transitions of CLKB must occur while RS1 is LOW.

I ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM

pin. If RTM is LOW, then a LOW on this pin initializes the FIFO read and write pointers to the first location

of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently

selected bus size, endian arrangement, programming method (serial or parallel), and programmable

flag settings are all retained. If RTM is HIGH, then a LOW on this pin performs a Retransmit and initializes

the read pointer only, to the first memory location.

I This pin is used in conjunction with the RT pin. When RTM is HIGH a Retransmit is performed when

RT is taken HIGH.

I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin

when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size

and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH

transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH

transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.

NOTE:

1. FS2, BM and Size inputs are not TTL compatible. These inputs should be tied to GND or VCC.

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