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IR1152S

FIXED 66kHz FREQUENCY, µPFC ONE CYCLE CONTROL PFC IC WITH BROWN-OUT PROTECTION

International Rectifier 

IR1152S

IR1152 General Description

Programmable Soft Start

The soft start process controls the rate of rise of the

voltage feedback loop error signal thus providing a

linear increase of the RMS input current that the

PFC converter will admit. The soft start time is

essentially controlled by voltage error amplifier

compensation components selected and is

therefore user programmable to some degree

based on desired voltage feedback loop crossover

frequency.

Gate Drive Capability

The gate drive output stage of the IC is a totem

pole driver with 750mA peak current drive

capability. The gate drive is internally clamped at

13V (Typ). Gate drive buffer circuits can be easily

driven with the GATE pin of the IC to suit any

system power level.

System Protection Features

IR1152 protection features include Brown-out

protection (BOP), Open-loop protection (OLP),

Overvoltage protection (OVP), Cycle-by-cycle peak

current limit (IPK LIMIT), Soft-current limit and VCC

under voltage lock-out (UVLO).

- BOP is based on direct input line sensing using a

resistor divider/RC filter network. If BOP pin falls

below the Brown-out protection threshold VBOP, a

Brown-out situation is immediately detected and

the following response is executed - the gate drive

pulse is disabled, VCOMP is actively discharged

and IC is pushed into Stand-by Mode. The IC re-

enters normal operation only after BOP pin

exceeds VBOP(EN). During start-up the IC is held in

Stand-by Mode until this pin exceeds VBOP(EN).

- OLP is activated whenever the VFB pin voltage

falls below VOLP threshold. Once open loop is

detected the following response is immediately

executed - the gate drive is immediately disabled,

VCOMP is actively discharged and the IC is

pushed into Stand-by mode. There is no voltage

hysteresis associated with this feature. During

start-up the IC is held in Stand-by Mode until VFB

exceeds VOLP.

- OVP feature in IR1152 is "dual" and "dedicated".

There are 2 overvoltage comparators in IR1152 -

marked OVP(OVP) and OVP(VFB) in the block

diagram. Both these are identical in design, reference

the exact same thresholds and thus identical in

operation. The non-inverting input of OVP(VFB)

comparator is on the VFB pin while that of the

OVP(OVP) comparator is on the OVP/EN pin. When

either or both of the pin voltages exceeds VOVP, an

overvoltage situation is detected and the gate drive is

immediately terminated. The gate drive is re-enabled

only after both pin voltages are below VOVP(RST). The

redundancy offered by the 2 comparators and use of

a dedicated OVP/EN pin ensures the best possible

system overvoltage protection against extremes of

situations such as component failures, pin-to-pin

shorts etc.

- Soft-current limit is an output voltage fold-back type

protection feature encountered when the PFC

converter input current exceeds to a point where the

Vm voltage saturates. As mentioned earlier, the

amplitude of input current is directly proportional to

Vm, the error voltage of the feedback loop. Vm is

clamped to a certain maximum voltage inside the IC

(given by VCOMP,EFF parameter in datasheet). If the

input current causes the Vm voltage to saturate at its

maximum value, then any further increase in input

current will cause the duty cycle to droop which

immediately forces the VOUT voltage of the PFC

converter to fold-back. Since the highest current is at

the peak of the AC sinusoid, the droop in duty cycle

commences at the peak of the AC sinusoid when the

soft-current limit is encountered. In most converters,

the design of the current sense resistor is performed

based on soft-current limit (i.e. Vm saturation) and at

the system condition which demands highest input

current (minimum VAC & maximum POUT).

- Cycle-by-cycle peak current limit protection

instantaneously turns-off the gate output whenever

the ISNS pin voltage exceeds VISNS(PK) threshold in

magnitude. The gate drive is held in the low state as

long as the overcurrent condition persists. The gate

drive is re-enabled when the magnitude of ISNS pin

voltage falls below the VISNS(PK) threshold. This

protection feature incorporates a leading edge

blanking circuit to improve noise immunity.

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