IS25LQ040-JPLE(2012) 查看數據表（PDF） - Integrated Silicon Solution

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IS25LQ040-JPLE
(Rev.:2012)

4 Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface

Integrated Silicon Solution 

DEVICE OPERATION (CONTINUED)

Figure 16. Fast Read Dual I/O Sequence (without command decode cycles)

CE#

IS25LQ040

SCK

IO0

IO1

0 1 2 3 10 11 12 13 14 15 16 17 18 19 20 21

...

3 - BYTE ADDRESS

22 21 19

... 2 0

MODE BITS

64

23 22 20

... 3 1 7 5

6 42 06 4

DATA OUT 1

DATA OUT 2

753 175

FRQO COMMAND (FAST READ QUAD OUTPUT) OPERATION

The FRQO instruction is used to read memory data on simultaneously the second bit is output on IO2, the

four output pins each at up to a 100 MHz clock.

third bit is output on IO1, etc.

The FRQO instruction code is followed by three

The first byte addressed can be at any memory

address bytes (A23 – A0) and a dummy byte (8

location. The address is automatically incremented

clocks), transmitted via the SI line, with each bit

after each byte of data is shifted out. When the highest

latched-in during the rising edge of SCK. Then the first address is reached, the address counter will roll over to

data byte addressed is shifted out on the IO3, IO2, IO1 the 000000h address, allowing the entire memory to be

and IO0 lines, with each group of four bits shifted out at read with a single FRQO instruction. FRQO instruction

a maximum frequency fCT, during the falling edge of is terminated by driving CE# high (VIH). If a FRQO

SCK. The first bit (MSb) is output on IO3, while

instruction is issued while an Erase, Program or Write

cycle is in process (BUSY=1) the instruction is ignored

and will not have any effects on the current cycle

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

21

09/13/2012

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