LX64EC 查看數據表（PDF） - Lattice Semiconductor

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LX64EC

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

Figure 13. Operation in FIFO Mode2

GRP

GDX Block 1

FIFO

ispGDX2 Family Data Sheet

SERDES

Pre-Assigned Pins

Input

Reg/

Latch

Output

Reg/

Latch

Input

Reg/

Latch

Delay

10

DOUT

RCLK

RE

10

DIN

RXD

Parallel

Data

Serial

Data In

(SIN)

10

PT-CLK/CE(0:3)

TXD Serial

Parallel Data Out

Data (SOUT)

WE

GCLK/CE(0:3)

WCLK

RECCLK

Input

Reg/

Latch

Output

Reg/

Latch

FULL

EMPTY

Output

Reg/

Latch

FIFORSTb

Notes:

1. For clarity, only a portion of the GDX Block is shown.

2. Some signals share pins. See Logic Signal Connections tables for details.

SYDT

CDRRSTb

POR

RESETb

CAL

16

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