LX64EC 查看數據表（PDF） - Lattice Semiconductor

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LX64EC

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

Figure 15. Operation in SERDES Only Mode1, 2

GRP

GDX Block

FIFO

ispGDX2 Family Data Sheet

SERDES

Pre-Assigned Pins

Input

Reg/

Latch

Output

Reg/

Latch

Input

Reg/

Latch

Delay

DOUT

RCLK

RE

10

DIN

RXD

Parallel

Data

Serial

Data In

(SIN)

10

PT-CLK/CE(0:3)

TXD Serial

Parallel Data Out

Data (SOUT)

WE

GCLK/CE(0:3)

WCLK

RECCLK

CAL

Input

Reg/

Latch

Output

Reg/

Latch

Output

Reg/

Latch

Notes:

1. Some pins shared. See Logic Signal

Connections table for details.

2. For SERDES only mode programmable bit

holds FIFO in reset. Input registers used for

DOUT, and RECCLK configured as

latches and held in pass through.

FULL

EMPTY

FIFORSTb

SYDT

CDRRSTb

POR

RESETb

19

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