IT8705F 查看數據表（PDF） - ITE Tech. INC.

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IT8705F

Simple Low Pin Count Input / Output (Simple LPC I/O)

ITE Tech. INC. 

Contents

Table 9-8. Data Rate Select Register (DSR)..................................................................................................... 96

Table 9-9. Data Register (FIFO)........................................................................................................................ 97

Table 9-10. Digital Input Register (DIR) ............................................................................................................ 97

Table 9-11. Diskette Control Register (DCR) .................................................................................................... 97

Table 9-12. Status Register 0 (ST0).................................................................................................................. 98

Table 9-13. Status Register 1 (ST1).................................................................................................................. 99

Table 9-14. Status Register 2 (ST2).................................................................................................................. 99

Table 9-16. Status Register 3 (ST3)................................................................................................................ 100

Table 9-17. Command Set Symbol Descriptions ............................................................................................ 101

Table 9-18. Command Set Summary .............................................................................................................. 103

Table 9-19. Effects of MT and N Bits............................................................................................................... 111

Table 9-20. SCAN Command Result............................................................................................................... 113

Table 9-21. VERIFY Command Result............................................................................................................ 114

Table 9-22. Interrupt Identification................................................................................................................... 117

Table 9-23. HUT Values (ms).......................................................................................................................... 117

Table 9-24. SRT Values (ms) .......................................................................................................................... 117

Table 9-25. HLT Values................................................................................................................................... 117

Table 9-26. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands........................ 118

Table 9-27. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands... 118

Table 9-28. Serial Channel Registers.............................................................................................................. 119

Table 9-29. Interrupt Enable Register Description .......................................................................................... 120

Table 9-30. Interrupt Identification Register .................................................................................................... 121

Table 9-31. FIFO Control Register Description ............................................................................................... 122

Table 9-32. Receiver FIFO Trigger Level Encoding........................................................................................ 122

Table 9-33. Baud Rates Using (24 MHz ÷ 13) Clock....................................................................................... 123

Table 9-34. Line Control Register Description ................................................................................................ 124

Table 9-35. Stop Bits Number Encoding ......................................................................................................... 124

Table 9-36. Modem Control Register Description ........................................................................................... 125

Table 9-37. Line Status Register Description .................................................................................................. 125

Table 9-39. Modem Status Register Description............................................................................................. 127

Table 9-41. Reset Control of Registers and Pinout Signals ............................................................................ 128

Table 9-42. Parallel Port Connector in Different Modes.................................................................................. 130

Table 9-43. Address Map and Bit Map for SPP and EPP Modes ................................................................... 131

Table 9-44. Bit Map of the ECP Registers....................................................................................................... 134

Table 9-45. ECP Register Definitions.............................................................................................................. 134

Table 9-46. ECP Mode Descriptions ............................................................................................................... 135

Table 9-47. ECP Pin Descriptions ................................................................................................................... 135

Table 9-49. Extended Control Register (ECR) Mode and Description............................................................ 137

Table 9-50. List of CIR Registers .................................................................................................................... 142

ix

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