74F1763 查看數據表（PDF） - Philips Electronics
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74F1763 Datasheet PDF : 16 Pages
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Philips Semiconductors
Intelligent DRAM controller (IDC)
33.34 MHz
PU
1, 7, 9, 10
CP
F160A
Q0
Q2
MEMORY
SELECT
(FROM ADDRESS DECODER
AS
A3
A2
A4–A12
A13–A21
DQ
C
D
CQ
PU
CP
PRECHRG
RCP
RAS
HLROW
REQ
74F1763
DRAM
CONTROLLER
PAGE
CAS
ALE
CA9
RA9
RA0–8
CA0–8
MA0–MA9
Product specification
74F1763
16.67 MHz
CPU CLOCK
RAS
MA0–MA9
A0
A1
SIZ0
SIZ1
CAS0
CAS1
PLD
10
CAS2
CAS3
STERM
DQ
CBACK
CBREQ
DSACK0
DSACK1
CQ
DS
Q3
F164
CP
MR
DQ
C
SF01407
Figure 5. 16.67 MHz 68030 interface with 74F1763 for cache burst mode support using 4Mbytes of 100nsec. nibble-mode DRAMs
(Four 32 bit words read to or written from cache in only clock cycles
1999 Jan 08
12
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