LB11872H 查看數據表（PDF） - SANYO -> Panasonic
零件编号
产品描述 (功能)
生产厂家
LB11872H Datasheet PDF : 11 Pages
| |||
LB11872H
Allowable Operating Conditions at Ta = 25°C
Parameter
Supply voltage range
6.3 V regulator-voltage output current
LD pin applied voltage
LD pin output current
FGS pin applied voltage
FGS pin output current
Symbol
VCC
IREG
VLD
ILD
VFG
IFG
Conditions
Ratings
Unit
10 to 28
V
0 to -20
mA
0 to 28
V
0 to 15
mA
0 to 28
V
0 to 10
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24V
Parameter
Symbol
Conditions
Supply current 1
ICC1
Supply current 2
ICC2
Output saturation voltages VAGC = 3.5V
SOURCE (1)
VSAT1-1
SOURCE (2)
VSAT1-2
SINK (1)
VSAT2-1
SINK (2)
VSAT2-2
Output leakage current
6.3V Regulator-voltage output
IO (LEAK)
Stop mode
Start mode
IO = 0.5A, RF = 0Ω
IO = 1.0A, RF = 0Ω
IO = 0.5A, RF = 0Ω
IO = 1.0A, RF = 0Ω
VCC = 28V
Ratings
Unit
min
typ
max
5
7
mA
17
22
mA
1.7
2.2
V
2.0
2.7
V
0.4
0.9
V
1.0
1.7
V
100
μA
Output voltage
VREG
5.90
6.25
6.60
V
Voltage regulation
Load regulation
Temperature coefficient
ΔVREG1
ΔVREG2
ΔVREG3
VCC = 9.5 to 28V
Iload = -5 to -20mA
Design target value*1
50
100
mV
10
60
mV
0
mV/°C
Hall amplifier block
Input bias current
IB (HA)
Differential input : 50mVp-p
2
10
μA
Differential input voltage range
Common-phase input voltage range
Input offset voltage
VHIN
VICM
VIOH
SIN wave input
Differential input : 50mVp-p
Design target value*1
50
*600 mVp-p
2.0
VCC-2.5
V
-20
20
mV
FG amplifier and schmitt block (IN1)
Input amplifier gain
GFG
5
Times
Input hysteresis (high to low)
VSHL
0
mV
Input hysteresis (low to high)
VSLH
-10
mV
Hysteresis width
VFGL
Input conversion
4
7
12
mV
Low-voltage protection circuit
Operating voltage
VSD
8.4
8.8
9.2
V
Hysteresis width
ΔVSD
0.2
0.4
0.6
V
Thermal protection circuit
Thermal shutdown operating
TSD
Design target value*1 (junction temperature)
150
180
°C
temperature
Hysteresis width
ΔTSD
Design target value*1 (junction temperature)
40
°C
Current limiter operation
Acceleration limit voltage
VRF1
0.53
0.59
0.65
V
Deceleration limit voltage
VRF2
0.32
0.37
0.42
V
Error amplifier
Input offset voltage
VIO (ER)
Design target value*1
-10
10
mV
Input bias current
High-level output voltage
Low-level output voltage
DC bias level
IB (ER)
VOH (ER)
VOL (ER)
VB (ER)
IOH = -500μA
IOL = 500μA
-1
VREG-1.2 VREG-0.9
0.9
-5% 1/2VREG
1
μA
V
1.2
V
5%
V
Note* : Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input. amplitudes should be held to under 350mVp-p.
*1 : This parameter is a design target value and is not measured.
Continued on next page.
No.7257-2/11
Share Link: 