LC72708E 查看數據表（PDF） - SANYO -> Panasonic

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LC72708E

FM Multiplex Broadcast Reception IC for Mobile VICS Systems

SANYO -> Panasonic 

LC72708E

Control Register

0

Control register

1

2

3

4

5

6

7

VEC HALT EC STOP SYNC RST INT MOVE DO MOVE CRC4 RST

Bit

VEC HALT

2

(Vertical error correction stop)

EC STOP

3

(Error correction stop)

SYNC RST

4

(Synchronization block reset)

INT MOVE

5

(INT type)

DO MOVE

6

(DO pin operation)

CRC4 RST

7

(Layer 4 CRC)

Note: Bits 0 and 1 are unused.

Function

Initial value

L Vertical correction and second horizontal correction: enabled

L

H Vertical correction and second horizontal correction: disabled

L All functions operate

L

H Only the MSK detection and synchronization regeneration circuits operate

L Normal operation

L

H Only the synchronization circuit is reset

L Only the correction complete, layer 2 CRC complete, and data received while synchronized are output.

L

H All data is output. (Operation identical to that of the LC72700)

L The high-level (high-impedance) state is held at times other than data output

L

H The DO pin changes with the INT pin. (Operation identical to that of the LC72700)

L Normal operation

L

H The layer 4 CRC circuit is reset to its initial state.

Detailed Descriptions

• VEC HALT

Setting this flag stops all IC operations related to vertical and second horizontal correction. Data output is limited to

data following the first horizontal correction.

• EC STOP

This flag stops all operations (including RAM access) related to error correction and all data output operations. While

all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data input

circuit, and the layer 4 CRC circuit continue to operate in this mode.

• SYNC RST

Clears the synchronization state and the synchronization protection state in the synchronization block and sets that

block to the unsynchronized state. This allows quick frame synchronization pull in when, during receiver tuning

operations, the frame period of the new reception data after station selection is displaced. While this flag is used for

initialization of synchronization related circuits, it does not initialize the number of allowed BIC errors, the block

synchronization forward and backward protection settings, and the registers of frame synchronization forward and

backward protection settings. During the synchronization block reset, the INT signal is not output and the DO pin

outputs a high level (high impedance). Since this flag is not automatically reset to 0, applications must send data again

to set it to 0.

• INT MOVE

The data output by this IC is fully corrected, and only data received during both block and frame synchronization is

output. (The layer 2 CRC check is included.) This flag must be set to acquire all data in the same manner as the

LC72700.

• DO MOVE

In the LC72700, the DO pin output was linked to and changed with the INT signal so that it could be used in place of

the INT CPU interrupt signal. Set this flag to use that function.

No. 5875-8/15

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