LC7861KE 查看數據表（PDF） - SANYO -> Panasonic
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LC7861KE Datasheet PDF : 18 Pages
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LC7861KE
Pin Functions
No.
Name
1
TEST1
2
AO
3
AI
4
PDO
5
VSS
6
EFMO
7
EFMO
8
EFMIN
9
TEST2
10
CLV+
11
CLV–
12
V/P
13
FOCS
14
FST
15
FZD
16
HFL
17
TES
18
PCK
19
FSEQ
20
TOFF
21
TGL
22
THLD
23
TEST3
24
VDD
25
JP+
26
JP–
27
DEMO
28
TEST4
29
EMPH
30
DFOFF
31
SMP2
32
SMP1
33
LRCLK
34
SMP
35
DFOUT
36
DACLK
37
DFIN
38
LRSY
39
CK2
40 ROMOUT
41
C2FCLK
42
C2F
43
DOUT
44
SBSY
45
EFLG
46
PW
47
SFSY
48
SBCK
49
FSX
50
WRQ
51
RWC
52
SQOUT
I/O
Description
I
LSI test pin. Normally left open.
O
I
Inputs for the LA9210 internal VCO output. (8.6436 MHz)
Set up PDO so that the frequency increases when the EFM signal and the phase output are positive.
O
— GND
O
O
Supply an HF signal with a 1 to 2 Vp-p level to EFMIN. EFMO and EFMO output EFM signals with opposite phases
that passed through an amplitude limiter circuit. These are used for slice level control.
I
I
LSI test pin. Normally left open.
O
Disk motor control output.
O
O Outputs a high level during CLV rough servo and a low level during phase control.
O
O
FOCS outputs a high level when the focus servo is off. The lens is lowered by FST, and when FOCS is high the lens is
raised gradually. FOCS is reset when an FZD input occurs. These are used for focus pull-in.
I
I
I
PCK is the 4.3218 monitor pin.
O It outputs a high level when the synchronization (positive FS) detected from the EFM signal matches the counter
O
synchronization (interpolation FS). (The output is latched for a single frame.)
O
O The LC7861KE outputs a kick pulse from JP+ and JP– in response to a track jump command. A track jump of the
O specified number of tracks (1, 4, 16, 32, 64, and 128) is performed.
I
LSI test pin. Normally left open.
— +5 V
O
O
I
Sound output function for end product adjustment manufacturing steps.
I
LSI test pin. Normally left open.
O De-emphasis is required when high.
I
Digital filter on/off switch. Filtering is turned off on a high level input.
O
O
O Outputs for an external D/A converter. These include a latch signal, an L/R switching signal, and a sample and hold
O signal.
O
O
O LSI test pin. Normally left open.
O
O
O CD-ROM application output signals
O
O
O Digital output
O Subcode block synchronization signal
O C1, C2, single and double error correction monitor pin
O
O
SFSY is the subcode frame synchronization signal. The P, Q, R, S, T, U, V and W subcodes can be read out by
applying 8 clock cycles to SBCK.
I
O 7.35 kHz synchronization signal output
O
WRQ goes high when the subcode Q data passes the CRC check. An external controller can read out data from
I
SQOUT by monitoring this pin and applying a CQCK signal. Set M/L to low when data is required LSB first.
O
Continued on next page.
No. 4818-5/18
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