LFECP40E-4F900C 查看數據表（PDF） - Lattice Semiconductor

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LFECP40E-4F900C

LatticeECP/EC Family Data Sheet Introduction

Lattice Semiconductor 

LatticeECP/EC Family Data Sheet

Supplemental Information

October 2004

Preliminary Data Sheet

For Further Information

A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com.

• LatticeECP/EC sysIO Usage Guide (TN1056)

• ispTRACY Internal Logic Analyzer Guide (TN1054)

• LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049)

• Memory Usage Guide for LatticeECP/EC Devices (TN1051)

• LatticeECP/EC DDR Usage Guide (TN1050)

• Estimating Power Using Power Calculator for LatticeECP/EC Devices (TN1052)

• sysDSP/MAC Usage Guide (TN1057)

• LatticeECP/EC sysCONFIG Usage Guide (TN1053)

• IEEE 1149.1 Boundary Scan Testability in Lattice Devices

For further information on interface standards refer to the following web sites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

• PCI: ww.pcisig.com

© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

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Further Info_01.1

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