LFECP20E-5F900C 查看數據表（PDF） - Lattice Semiconductor

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LFECP20E-5F900C

LatticeECP/EC Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeECP/EC Family Data Sheet

Figure 2-21. MULTADDSUM

Shift Register B In

Shift Register A In

Multiplicand A0

Multiplier B0

Multiplicand A1

Multiplier B1

Multiplicand A2

Multiplier B2

Multiplicand A3

Multiplier B3

Signed

Addn0

Addn1

m

m

n

n

n

Input Data

Register B

n

m

Input Data m

Register A

n

m

m

n

n

Input Data

Register B

m

Input Data n

Register A

n

m

m

n

n

n

Input Data

Register B

n

m

Input Data m

Register A

n

m

m

n

n

m

Input Data m

Register A

Input Data

Register B

n

Input

Register

n

m

Pipeline

Register

Input

Register

Pipeline

Register

Input

Register

Pipeline

Register

Multiplier m+n

x

(default)

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Pipeline

Register

Add/Sub0

m+n

(default)

Multiplier

x

Pipeline

Register

m+n+1

SUM

m+n+2

Multiplier m+n

x

(default)

m+n+1

Pipeline

Register

Add/Sub1

m+n

(default)

Multiplier

x

Pipeline

Register

To Add/Sub0, Add/Sub1

To Add/Sub0

To Add/Sub1

Shift Register B Out

Shift Register A Out

Output

m+n+2

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset

and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)

one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and

Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)

at each input register, pipeline register and output register.

Signed and Unsigned with Different Widths

The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For

unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed

two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36

width is reached. Table 2-8 provides an example of this.

2-18

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