LFEC6E-5QN208I 查看數據表（PDF） - Lattice Semiconductor

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LFEC6E-5QN208I

LatticeECP/EC Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Figure 2-14. DCS Waveforms

CLK0

CLK1

Architecture

LatticeECP/EC Family Data Sheet

SEL

DCSOUT

sysMEM Memory

The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-

Kbit RAM, with dedicated input and output registers.

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-6.

Table 2-6. sysMEM Block Configurations

Memory Mode

Single Port

True Dual Port

Pseudo Dual Port

Configurations

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block

during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

2-12

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