LFECP20E-5F256C 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

LFECP20E-5F256C

LatticeECP/EC Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeECP/EC Family Data Sheet

Figure 2-16. Memory Core Reset

Memory Core

Q D SET

LCLR

Port A[17:0]

RSTA

Output Data

Latches

Q D SET

LCLR

Port B[17:0]

RSTB

GSRN

Programmable Disable

For further information about sysMEM EBR block, please see the the list of technical documentation at the end of

this data sheet.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-17. The GSR input to the

EBR is always asynchronous.

Figure 2-17. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becomes active.

These instructions apply to all EBR RAM and ROM implementations.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

sysDSP Block

The LatticeECP-DSP family provides a sysDSP block, making it ideally suited for low cost, high performance Digital

Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response

(FIR) filters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and

2-14

Share Link: