LFEC20E-4F672I 查看數據表（PDF） - Lattice Semiconductor
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LFEC20E-4F672I Datasheet PDF : 163 Pages
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Lattice Semiconductor
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-20. MAC sysDSP Element
Shift Register B In
Shift Register A In
Multiplicand
m
m
Multiplier
SignedAB
Addn
Accumsload
n
n
n
m
Input Data
m
Register A
Input Data
Register B
n
Input
Register
Input
Register
Input
Register
n
n
Pipeline
Register
Pipeline
Register
Pipeline
Register
Multiplier
x m+n
(default)
Pipeline
Register
To
Accumulator
To
Accumulator
To
Accumulator
Shift Register B Out
Shift Register A Out
Accumulator
m+n+16 bits
(default)
m+n+16 bits
(default)
Output
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Overflow
signal
MULTADD sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21
shows the MULTADD sysDSP element.
Figure 2-21. MULTADD
Shift Register B In
Shift Register A In
Multiplicand A0
m
m
Multiplier B0 n
n
n
m
Input Data m
Register A
Input Data
Register B
Multiplicand A1
n
m
n
m
Multiplier B1
Signed
Addn
n
n
m
Input Data m
Register A
Input Data
Register B
n
Input
Register
Input
Register
n
m
PipPeilpinee
RegRisetger
PipePliipnee
RegRisetger
Multiplier
x
Pipeline
Register
Multiplier
x
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
m+n
(default)
Add/Sub
m+n
(default)
m+n+1
(default)
m+n+1
(default)
Output
Pipeline
Register
To Add/Sub
To Add/Sub
Shift Register B Out
Shift Register A Out
2-17
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