LH7A400N0B000 查看數據表（PDF） - Sharp Electronics

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LH7A400N0B000

32 BIT SYSTEM ON CHIP

Sharp Electronics 

32-Bit System-on-Chip

LH7A400

Table 1. Functional Pin List (Cont’d)

PBGA CABGA

PIN PIN

SIGNAL

J7

G3 UARTRX2

H4

J3 SSPCLK

J1

J6 SSPRX

J2

J7 SSPTX

J3

J2

SSPFRM/

nSSPFRM

F6

G2 COL0

F5

G1 COL1

G1

H3 COL2

G2

H5 COL3

G4

H6 COL4

G5

H7 COL5

H1

H2 COL6

H2

H1 COL7

H3

J1 TBUZ

C3

F5 MEDCHG

P11 T14 WIDTH0

R12 T15 WIDTH1

D1

E3 BATOK

D2

F6 nBATCHG

A1

E5 TDI

B1

C2 TCK

B2

D3 TDO

C1

C1 TMS

T12 P15 nTEST0

R15 P13 nTEST1

DESCRIPTION

RESET

STATE

UART2 Receive Data Input. This pin is an output

for JTAG boundary scan only.

Input

Synchronous Serial Port Clock

LOW

Synchronous Serial Port Receive

Input

Synchronous Serial Port Transmit

LOW

Synchronous Serial Port Frame Sync

Input:

nSSPFRM

STANDBY OUTPUT

STATE

DRIVE

Input

LOW

Input

LOW

Input

8 mA

8 mA

8 mA

Keyboard Interface

HIGH

HIGH

8 mA

Timer Buzzer (254 kHz MAX.)

LOW

LOW

Boot Device Media Change. Used with the

WIDTH0 and WIDTH1 pins to specify boot mem- Input (Schmitt) Input

ory device.

External Memory Width Pins. Also, used with

MEDCHG to specify the boot memory device size.

Input (Schmitt)

Input

Battery OK

Input (Schmitt) Input

Battery Change

Input (Schmitt) Input

JTAG Data In. This signal is internally pulled-up Input with

to VDD.

Pull-up

Input with

Pull-up

JTAG Clock. This signal should be externally

pulled-up to VDD.

Input

Input

JTAG Data Out. This signal should be externally

pulled up to VDD with a 33 kΩ resistor.

Input

No Change

JTAG Test Mode select. This signal is internally Input with

pulled-up to VDD.

Pull-up

Input with

Pull-up

Test Pin 0. Internally pulled up to VDD. For Normal

mode, leave open. For JTAG mode, tie to GND.

See Table 2.

Input with

Pull-up

Input with

Pull-up

Test Pin 1. internally pulled up to VDD. For Normal Input with

and JTAG mode, leave open. See Table 2.

Pull-up

Input with

Pull-up

8 mA

4 mA

NOTES: *Signals beginning with ‘n’ are Active LOW.

Table 2. nTest Pin Function

MODE

JTAG

Normal

nTEST0

0

1

nTEST1

1

1

nURESET

1

x

Preliminary Data Sheet

12/8/03

11

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