LM3S817-IRN50-B0T 查看數據表（PDF） - Unspecified
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LM3S817-IRN50-B0T Datasheet PDF : 379 Pages
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List of Registers
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088.................................... 233
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C................................ 233
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ................. 234
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ............................................ 235
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ................................... 235
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................... 235
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ............................................................ 236
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 238
Register 1: UART Data (UARTDR), offset 0x000 ...................................................................................... 245
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 247
Register 3: UART Flag (UARTFR), offset 0x018 ....................................................................................... 249
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 251
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 252
Register 6: UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 253
Register 7: UART Control (UARTCTL), offset 0x030................................................................................. 255
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 256
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 257
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 259
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 260
Register 12: UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 261
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 262
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 263
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 264
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 265
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 266
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 267
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 268
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 269
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 270
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 271
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 272
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 273
Synchronous Serial Interface (SSI) ............................................................................................. 274
Register 1: SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 286
Register 2: SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 288
Register 3: SSI Data (SSIDR), offset 0x008 .............................................................................................. 290
Register 4: SSI Status (SSISR), offset 0x00C ........................................................................................... 291
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 292
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 293
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 294
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 295
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 296
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 297
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 298
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 299
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 300
14
May 4, 2007
Preliminary
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