LM3S817-IQN25-A2T 查看數據表（PDF） - Unspecified
零件编号
产品描述 (功能)
生产厂家
LM3S817-IQN25-A2T Datasheet PDF : 379 Pages
| |||
List of Registers
General-Purpose Input/Outputs (GPIOs) .................................................................................... 115
Register 1: GPIO Data (GPIODATA), offset 0x000 ................................................................................... 123
Register 2: GPIO Direction (GPIODIR), offset 0x400 ................................................................................ 124
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404......................................................................... 125
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408.............................................................. 126
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C....................................................................... 127
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410.......................................................................... 128
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414.............................................................. 129
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ........................................................ 130
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C....................................................................... 131
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ................................................. 132
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500.............................................................. 133
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504.............................................................. 134
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508.............................................................. 135
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C............................................................... 136
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ...................................................................... 137
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514.................................................................. 138
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518...................................................... 139
Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C ............................................................. 140
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ........................................... 141
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ........................................... 142
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ........................................... 143
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC........................................... 144
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ........................................... 145
Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ............................................ 146
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ........................................... 147
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC........................................... 148
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .............................................. 149
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .............................................. 150
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .............................................. 151
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC.............................................. 152
General-Purpose Timers .............................................................................................................. 153
Register 1: GPTM Configuration (GPTMCFG), offset 0x000..................................................................... 165
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 .................................................................. 166
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 .................................................................. 167
Register 4: GPTM Control (GPTMCTL), offset 0x00C............................................................................... 168
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .................................................................... 170
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .......................................................... 172
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ..................................................... 173
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024..................................................................... 174
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ...................................................... 175
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C...................................................... 176
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ....................................................... 177
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ....................................................... 178
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038.............................................................. 179
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ............................................................. 180
12
May 4, 2007
Preliminary
Share Link: 