LM3S817-IQN50-A0T 查看數據表（PDF） - Unspecified
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LM3S817-IQN50-A0T Datasheet PDF : 379 Pages
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LM3S817 Data Sheet
Register 15:
Register 16:
Register 17:
Register 18:
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................ 181
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................ 182
GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................... 183
GPTM TimerB (GPTMTBR), offset 0x04C .............................................................................. 184
Watchdog Timer............................................................................................................................ 185
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ............................................................................ 188
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ......................................................................... 189
Register 3: Watchdog Control (WDTCTL), offset 0x008............................................................................ 190
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 191
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 192
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 193
Register 7: Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 194
Register 8: Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 195
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 196
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 197
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 198
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 199
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 200
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 201
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 202
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 203
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 204
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 205
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 206
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 207
Analog-to-Digital Converter (ADC).............................................................................................. 208
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .................................................. 214
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004................................................................. 215
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ............................................................................ 216
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C........................................................ 217
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 .................................................................. 218
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ...................................................... 219
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ................................................................ 220
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020.................................................. 221
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ..................................... 222
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ...................................................... 223
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040.................. 224
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044............................................. 226
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048.................................... 228
Register 14: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C................................ 229
Register 15: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060.................. 230
Register 16: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064............................................. 231
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068.................................... 231
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C................................ 231
Register 19: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080.................. 232
Register 20: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084............................................. 233
May 4, 2007
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Preliminary
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