LM3S817-IRN25-A1 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

LM3S817-IRN25-A1

Microcontroller

Unspecified 

Architectural Overview

• Programmable periodic timer

• Real-Time Clock when using an external 32.768-KHz clock as the input

• User-enabled stalling in periodic and one-shot mode when the controller asserts the

CPU Halt flag during debug

• ADC event trigger

– 16-bit Timer modes:

• General-purpose timer function with an 8-bit prescaler

• Programmable one-shot timer

• Programmable periodic timer

• User-enabled stalling when the controller asserts CPU Halt flag during debug

• ADC event trigger

– 16-bit Input Capture modes:

• Input edge count capture

• Input edge time capture

– 16-bit PWM mode:

• Simple PWM mode with software-programmable output inversion of the PWM signal

„ ARM FiRM-compliant Watchdog Timer

– 32-bit down counter with a programmable load register

– Separate watchdog clock with an enable

– Programmable interrupt generation logic with interrupt masking

– Lock register protection from runaway software

– Reset generation logic with an enable/disable

– User-enabled stalling when the controller asserts the CPU Halt flag during debug

„ Synchronous Serial Interface (SSI)

– Master or slave operation

– Programmable clock bit rate and prescale

– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments

synchronous serial interfaces

– Programmable data frame size from 4 to 16 bits

– Internal loopback test mode for diagnostic/debug testing

„ UART

– Two fully programmable 16C550-type UARTs

– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt

service loading

– Programmable baud-rate generator with fractional divider

– Programmable FIFO length, including 1-byte deep operation providing conventional

double-buffered interface

22

May 4, 2007

Preliminary

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