LPC1102UK(2011) 查看數據表（PDF） - NXP Semiconductors.
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LPC1102UK
(Rev.:2011)
(Rev.:2011)
NXP Semiconductors.
LPC1102UK Datasheet PDF : 39 Pages
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NXP Semiconductors
LPC1102
32-bit ARM Cortex-M0 microcontroller
10.5 I/O pins
Table 13. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD 3.6 V.
Symbol
Parameter
Conditions
Min
tr
rise time
pin
3.0
configured as
output
tf
fall time
pin
2.5
configured as
output
[1] Applies to standard port pins and RESET pin.
Typ
Max
Unit
-
5.0
ns
-
5.0
ns
10.6 SPI interfaces
Table 14. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter
Conditions
Min
Typ
SPI master (in SPI mode)
Tcy(clk)
clock cycle time
when only receiving [1] 50
-
when only transmitting [1] 40
tDS
data set-up time
in SPI mode
[2]
15
-
2.4 V VDD 3.6 V
2.0 V VDD < 2.4 V [2] 20
1.8 V VDD < 2.0 V [2] 24
-
tDH
data hold time
in SPI mode
[2]
0
-
tv(Q)
data output valid time in SPI mode
[2]
-
-
th(Q)
data output hold time in SPI mode
[2]
0
-
SPI slave (in SPI mode)
Tcy(PCLK)
tDS
tDH
tv(Q)
th(Q)
PCLK cycle time
data set-up time
in SPI mode
data hold time
in SPI mode
data output valid time in SPI mode
data output hold time in SPI mode
20
-
[3][4] 0
-
[3][4] 3 Tcy(PCLK) + 4 -
[3][4] -
-
[3][4] -
-
Max
-
-
-
-
10
-
-
-
-
3 Tcy(PCLK) + 11
2 Tcy(PCLK) + 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = 40 C to 85 C.
[3] Tcy(clk) = 12 Tcy(PCLK).
[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
LPC1102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 24 June 2011
© NXP B.V. 2011. All rights reserved.
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