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MAX120CAG 查看數據表(PDF) - Maxim Integrated

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MAX120CAG Datasheet PDF : 15 Pages
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MAX120/MAX122
500ksps, 12-Bit ADCs with Track/Hold
and Reference
Figure 13. Using MAX120 with FIFO Memory
Digital-Bus Noise
If the ADC’s data bus is active during a conversion,
coupling from the data pins to the ADC comparator can
cause errors. Using slow-memory mode (mode 3) avoids
this problem by placing the µP in a wait state during the
conversion. If the data bus is active during the conversion
in either mode 1 or 4, use three-state drivers to isolate the
bus from the ADC.
In ROM mode (mode 4), considerable digital noise is
generated in the ADC when RD or CS go high, disabling
the output buffers after a conversion is started. This noise
can cause errors if it occurs at the same instant the SAR
latches a comparator decision. To avoid this problem, RD
and CS should be active for less than 1 clock cycle. If
this is not possible, RD or CS should go high coinciding
with CLKIN’s falling edge, since the comparator output is
always latched at CLKIN’s rising edge
Layout, Grounding, and Bypassing
For best system performance, use PCBs with separate
analog and digital ground planes. Wire­wrap boards are
not recommended. The two ground planes should be tied
together at the low-impedance power-supply source, as
shown in Figure 14.
The board layout should ensure that digital and analog
signal lines are kept separate from each other as much as
possible. Do not run analog and digital (especially clock)
lines parallel to one another.
The ADC’s high-speed comparator is sensitive to high­
frequency noise in the VDD and VSS power supplies.
Bypass these supplies to the analog ground plane with
0.1µF and 10µF bypass capacitors. Minimize capacitor
lead lengths for best noise rejection. If the +5V power
supply is very noisy, connect a 5Ω resistor, as shown in
Figure 14. Figure 15 shows the negative power-supply
(VSS) rejection vs. frequency. Figure 16 shows the posi-
tive power-supply (VDD) rejection vs. frequency, with and
without the optional 5Ω resistor.
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