MAX122ACAG 查看數據表（PDF） - Maxim Integrated

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MAX122ACAG

500ksps, 12-Bit ADCs with Track/Hold and Reference

Maxim Integrated 

MAX120/MAX122

500ksps, 12-Bit ADCs with Track/Hold

and Reference

Pin Description (continued)

PIN

6

7–11, 13–19

12

20

21

NAME

AGND

D11–D0

DGND

CONVST

CLKIN

FUNCTION

Analog Ground

Three-State Data Outputs D11 (MSB) to D0 (LSB)

Digital Ground

Convert Start Input. Initiates conversions on its falling edge.

Clock Input. Drive with TTL-compatible clock from 0.1MHz to 8MHz (MAX120), 0.1MHz to 5MHz

(MAX122)

Interrupt or Busy Output. Indicates converter status. If MODE is connected to VDD, configure

22

INT/BUSY for an INT output. If MODE is open or connected to DGND, configure for a BUSY output. See

operational diagrams.

23

CS

Chip-Select Input, Active-Low. When RD is low, enables the three-state outputs. If CONVST and

RD are low, a conversion is initiated on the falling edge of CS.

24

RD

Read Input, Active-Low. When CS is low, RD enables the three-state outputs. If CONVST and CS

are low, conversion is initiated on the falling egde of RD.

Detailed Description

ADC Operation

The MAX120/MAX122 use successive approximation and

input T/H circuitry to convert an analog signal to a series

of 12-bit digital-output codes. The control logic interfaces

easily to most µPs, requiring only a few passive compo-

nents tor most applications. The T/H does not require an

external capacitor. Figure 3 shows the MAX120/MAX122

in the simplest operational configuration.

Analog Input Track/Hold

Figure 4 shows the equivalent input circuit, illustrating the

sampling architecture of the ADC’s analog comparator.

An internal buffer charges the hold capacitor to minimize

the required acquisition time between conversions. The

analog input appears as a 6kΩ resistor in parallel with a

10pF capacitor.

Between conversions, the buffer input is connected to AIN

through the input resistance. When a conversion starts,

the buffer input disconnects from AIN, thus sampling the

input. At the end of the conversion, the buffer input recon-

nects to AIN, and the hold capacitor once again charges

to the input voltage.

The T/H is in tracking mode whenever a conversion is

NOT in progress. Hold mode starts approximately 10ns

after a conversion is initiated. Variation in this delay from

one conversion to the next (aperture jitter) is typically

30ps. Figures 7 through 11 detail the T/H mode and inter-

face timing for the various interface modes.

Figure 1. Load Circuits for Access Time

Figure 2. Load Circuits for Bus-Relinquish Time

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