LT1800CS8 查看數據表（PDF） - Linear Technology
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LT1800CS8 Datasheet PDF : 18 Pages
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LT1800
APPLICATIONS INFORMATION
Circuit Description
The LT1800 has an input and output signal range that cov-
ers from the negative power supply to the positive power
supply. Figure 1 depicts a simplified schematic of the
amplifier. The input stage is comprised of two differential
amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4
that are active over the different ranges of common mode
input voltage. The PNP differential pair is active between the
negative supply to approximately 1.2V below the positive
supply. As the input voltage moves closer toward the posi-
tive supply, the transistor Q5 will steer the tail current I1 to
the current mirror Q6/Q7, activating the NPN differential
pair and the PNP pair becomes inactive for the rest of the
input common mode range up to the positive supply. Also
at the input stage, devices Q17 to Q19 act to cancel the bias
current of the PNP input pair. When Q1-Q2 are active, the
current in Q16 is controlled to be the same as the current
in Q1-Q2, thus the base current of Q16 is nominally equal
to the base current of the input devices. The base current
of Q16 is then mirrored by devices Q17-Q19 to cancel the
base current of the input devices Q1-Q2.
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail to rail constructs
the output stage. The capacitors C2 and C3 form the lo-
cal feedback loops that lower the output impedance at
high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1800 amplifier is offered in a small package, SOT-23,
which has a thermal resistance of 250°C/W, θJA. So there is
a need to ensure that the die’s junction temperature should
not exceed 150°C. Junction temperature TJ is calculated
from the ambient temperature TA, power dissipation PD
and thermal resistance θJA:
TJ = TA + (PD • θJA)
The power dissipation in the IC is the function of the sup-
ply voltage, output voltage and the load resistance. For
a given supply voltage, the worst-case power dissipation
PDMAX occurs at the maximum supply current and the
V+
+
I2
Q16
V+ V–
ESDD1
+IN
ESDD2
D6
D8
–IN
ESDD4
D5
D7
ESDD3
V– V+
Q17 Q18
Q19
V–
D1
D2
Q4 Q3
Q7
+
I1
Q5
VBIAS
Q1 Q2
D3
D4
Q6
R3 R4
R5
Q11 Q12
Q13
C2
+
I3
CC V–
Q15
OUT
BUFFER
AND
Q10
OUTPUT BIAS
Q9
Q8
R1 R2
C1
Q14
1800 F01
Figure 1. LT1800 Simplified Schematic Diagram
1800fa
12
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