LT3070MPUFDPBF 查看數據表（PDF） - Linear Technology
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LT3070MPUFDPBF Datasheet PDF : 24 Pages
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LT3070
PIN FUNCTIONS
VIOC (Pin 1): Voltage for In-to-Out Control. The IC in-
corporates a unique tracking function to control a buck
regulator powering the LT3070’s input. The VIOC pin is
the output of this tracking function that drives the buck
regulator to maintain the LT3070’s input voltage at VOUT +
300mV. This function maximizes efficiency and minimizes
power dissipation. See the Applications Information sec-
tion for more information on proper control of the buck
regulator.
PWRGD (Pin 2): Power Good. The PWRGD pin is an open-
drain NMOS output that is active low if any one of these
fault modes is detected:
• VOUT is less than 90% of VOUT(NOMINAL) on the rising
edge of VOUT
• VOUT drops below 85% of VOUT(NOMINAL) for more than
25μs
• Junction temperature exceeds 145°C
See the Applications Information section for more infor-
mation on PWRGD fault modes.
REF/BYP (Pin 3): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of ap-
proximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
function to the reference. See the Applications Information
section for more information on noise and output voltage
margining considerations.
GND (Pins 4, 9-14, 20, 26): Ground. All GND pins must
be tied together and to Pin 29, the exposed backside of
the package for proper thermal performance. These GND
pins are fused to the internal die attach paddle and exposed
package backside to optimize heat sinking and thermal
resistance performance.
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3070 requires a
bypass capacitor at IN to maintain stability and low input
impedance over frequency. A 47μF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizing input trace inductance optimizes performance.
Applications that operate with low VIN-VOUT differential
8
voltages and that have large, fast load transients may require
much higher input capacitor requirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor requirements.
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15μF is
required for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10μF + 4.7μF
+ 2.2μF provides excellent stability and load transient
response. Large load transient applications require larger
output capacitors to limit peak voltage transients. See the
Applications Information section for more information on
output capacitor requirements.
SENSE (Pin 19): Kelvin Sense for OUT. The SENSE pin is
the inverting input to the error amplifier. Optimum regulation
is obtained when the SENSE pin is connected to the OUT
pins of the regulator. In critical applications, the resistance
(RP) of PCB traces between the regulator and the load cause
small voltage drops, creating a load regulation error at the
point of load. Connecting the SENSE pin at the load instead
of directly to OUT eliminates this voltage error. Figure 1
illustrates this Kelvin-Sense connection method. Note that
the voltage drop across the external PCB traces adds to the
dropout voltage of the regulator. The SENSE pin input bias
current depends on the selected output voltage. SENSE
pin input current varies from 50μA typically at VOUT = 0.8V
to 300μA typically at VOUT = 1.8V.
+
VBIAS
+
VIN
BIAS
IN
SENSE
EN
OUT
VO2 LT3070
RP
VO1
PWRGD
VO0
MARGSEL
MARGTOL
VIOC
REF/BYP
GND
LOAD
RP
3070 F01
Figure 1. Kelvin Sense Connection
3070p
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