LT3587 查看數據表（PDF） - Linear Technology

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LT3587

High Voltage Monolithic Inverter and Dual Boost

Linear Technology 

LT3587

APPLICATIONS INFORMATION

Board Layout Consideration

As with all switching regulators, careful attention must be

paid to the PCB board layout and component placement.

To maximize efficiency, switch rise and fall times are made

as short as possible. To prevent electromagnetic interfer-

ence (EMI) problems, proper layout of the high frequency

switching path is essential.

In order to minimize magnetic field radiation, reduce the

parasitic inductance by keeping the traces that conduct high

switching currents short, wide and with minimal overall

loop area. These are typically the traces associated with

the switches. Figure 18 outlines the critical paths.

The voltage signals of the SW1, SW2 and SW3 pins have

rise and fall times of a few ns. Minimize the length and area

of all traces connected to the SW1, SW2 and SW3 pins

to reduce capacitive coupling between these fast nodes

and other circuitry. In particular, keep all the traces of the

feedback voltage pins (FB1, FB2, VFB3 and IFB3) away from

the switching node. Always use a ground plane under the

switching regulator to minimize interplane coupling.

Finally, place as much of the output capacitors of each

channel close to their respective CAP pins. Recommended

component placement is shown in Figure 19.

VVIN

C6

L1

DS1

SW1

CAP1

Q1 LT3587

GND

VVIN

C1 C6

L4

DS3

SW3

CAP3

Q3 LT3587

GND

VVIN

C6

C4

L2

C2

SW2

LT3587

Q2

GND

L3

DS2

VNEG

C7

Figure 18. High Current Paths

C7

L3

DS2

L2

C6

(OPT)

L4

RFB2

DS3

C4

RIFB3

CFB2

C5

C2

U1

RFB1

C6

C3

DS1

CFB1

L1

C1

VNEG

3587 F18

VIN

CAP3

VOUT3

VIN

VOUT1

C6

(OPT)

C6

(OPT)

VIN

CAP1

Figure 19. Recommended Component Placement

20

3587 F19

3587fc

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