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LTC1148CN

High Efficiency Synchronous Step-Down Switching Regulators

Linear Technology 

LTC1148

LTC1148-3.3/LTC1148-5

UU W U

APPLICATIO S I FOR ATIO

LTC1148 DC supply current is 160µA for no load, and

increases proportionally with load up to a constant

1.6mA after the LTC1148 series has entered continu-

ous mode. Because the DC bias current is drawn from

VIN, the resulting loss increases with input voltage. For

VIN = 10V the DC bias losses are generally less than 1%

for load currents over 30mA. However, at very low load

currents the DC bias current accounts for nearly all of

the loss.

2. MOSFET gate charge current results from switching the

gate capacitance of the power MOSFETs. Each time a

MOSFET gate is switched from low to high to low again,

a packet of charge dQ moves from VIN to ground. The

resulting dQ/dt is a current out of VIN which is typically

much larger than the DC supply current. In continuous

mode, IGATECHG = f (QN + QP). The typical gate charge

for a 0.1Ω N-channel power MOSFET is 25nC, and for

a P-channel about twice that value. This results in

IGATECHG = 7.5mA in 100kHz continuous operation, for

a 2% to 3% typical mid-current loss with VIN = 10V.

Note that the gate charge loss increases directly with

both input voltage and operating frequency. This is the

principal reason why the highest efficiency circuits

operate at moderate frequencies. Furthermore, it ar-

gues against using larger MOSFETs than necessary to

control I2R losses, since overkill can cost efficiency as

well as money!

3. I2R losses are easily predicted from the DC resistances

of the MOSFET, inductor, and current shunt. In continu-

ous mode the average output current flows through L

and RSENSE, but is “chopped” between the P-channel

and N-channel MOSFETs. If the two MOSFETs have

approximately the same RDS(ON), then the resistance of

one MOSFET can simply be summed with the resis-

tances of L and RSENSE to obtain I2R losses. For

example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω, and

RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This

results in losses ranging from 3% to 12% as the output

current increases from 0.5A to 2A. I2R losses cause the

efficiency to roll-off at high output currents.

Figure 5 shows how the efficiency losses in a typical

LTC1148 series regulator end up being apportioned.

100

I2R

GATE CHARGE

95

LTC1148 IQ

90

85

80

0.01

0.03 0.1 0.3

1

3

OUTPUT CURRENT (A)

LTC1148 • F05

Figure 5. Efficiency Loss

The gate charge loss is responsible for the majority of

the efficiency lost in the mid-current region. If Burst

Mode operation was not employed at low currents, the

gate charge loss alone would cause efficiency to drop to

unacceptable levels. With Burst Mode operation, the

DC supply current represents the lone (and unavoid-

able) loss component which continues to become a

higher percentage as output current is reduced. As

expected, the I2R losses dominate at high load currents.

Other losses including CIN and COUT ESR dissipative

losses, MOSFET switching losses, Schottky conduction

losses during dead time, and inductor core losses, gener-

ally account for less than 2% total additional loss.

Design Example

As a design example, assume VIN = 12V (nominal),

VOUT = 5V, IMAX = 2A, and f = 200kHz; RSENSE, CT and L

can immediately be calculated:

RSENSE = 100mV/2 = 0.05Ω

tOFF = (1/200kHz)[1 – (5/12)] = 2.92µs

CT = 2.92µs/[(1.3)(104)] = 220pF

LMIN = 5.1(105)0.05Ω(220pF)5V = 28µH

Assume that the MOSFET dissipations are to be limited to

PN = PP = 250mW.

If TA = 50°C and the thermal resistance of each MOSFET

is 50°C/ W, then the junction temperatures will be 63°C

12

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