LTC1159-5 查看數據表（PDF） - Linear Technology
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LTC1159-5 Datasheet PDF : 20 Pages
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LTC1159
LTC1159-3.3/LTC1159-5
APPLICATIO S I FOR ATIO
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE – pin to
subtract from the built-in 0.025V offset. An example of this
technique is shown in Figure 7. Two 100Ω resistors are
inserted in series with the leads from the sense resistor.
With the addition of R3, a current is generated through R1
causing an offset of:
) VOFFSET = VOUT
R1
R1 + R3
LTC1159
SENSE+ 9
SENSE – 8
1000pF
L
R2
100Ω
R1
100Ω
R3
1 RSENSE 2
3
4+
COUT
LTC1159 • F07
If VOFFSET > 0.025V, the minimum threshold will be
cancelled and Burst Mode operation is prevented from
occurring. Since VOFFSET is constant, the maximum load
current is also decreased by the same offset. Thus, to get
back to the same IMAX, the value of the sense resistor must
be reduced:
RSENSE
≈
75
IMAX
mΩ
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
the SENSE– and SENSE+ pins.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1159. These items are also illustrated graphically in
the layout diagram of Figure 8. Check the following in your
layout:
Figure 7. Suppressing Burst Mode Operation
1N4148
BOLD LINES INDICATE HIGH CURRENT PATHS
+
0.15µF
P-CHANNEL
+ CIN
VIN
D1
1µF
1
P-GATE
16
CAP
2
VIN
15
SHDN2
SHUTDOWN
0.1 µF
3
VCC
14
EXTVCC
4
P-DRIVE
5
VCC
13
N-GATE
12
PGND
5V EXTVCC
CONNECTION
6
CT
11
SGND
7
ITH
VFB 10
(SHDN1)
CT
3300pF 8 SENSE–
SENSE+ 9
1k
100pF
R1
R2
1000pF
N-CHANNEL
–
L
COUT
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY
–
3
1
VOUT
RSENSE
2
4
+
LTC1159 • F08
Figure 8. LTC1159 Layout Diagram (N and S Packages)
14
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